As integrated circuits (IC) have become smaller and more complex, IC designers use electronic design automation (EDA) software tools to design integrated circuits. Typically, the integrated circuit design process begins with a specification, which describes the functionality of the integrated circuit and may include a variety of performance requirements. Then, during a logic design phase, the logical implementation of the IC functionality is described using one of several hardware description languages such as Verilog or VHDL at the register transfer logic (RTL) level of abstraction. Typically, the EDA software tool synthesizes the abstract logic into a technology dependent netlist using a standard library from an IC manufacturer. The RTL can also describe the behavior of the circuits on the chip, as well as the interconnections to inputs and outputs.
After completion of the logic design phase, the IC undergoes a physical design phase. The physical design phase creates a semiconductor chip design from the RTL design and a library of available logic gates, and includes determining which logic gates to use, defining locations for the logic gates and interconnecting them. The physical design phase includes one or more of a number of steps, including the floorplan stage, placement and routing, Power Performance Area (PPA) violation determination, and Design Rule Change (DRC) violation determination. The physical design phase may include a number of iterations in order to meet these various design constraints (i.e., PPA, DRC, and similar constraints).
Across-chip layout uniformity is a characteristic of semiconductor devices. The semiconductor manufacturing process may yield semiconductor devices that possess physical variations across the device. Physical variations may lead to electrical variations in the semiconductor devices operation. The electrical variations include threshold voltage shifts and mismatched circuits resulting in semiconductor function failure.